The present invention relates to a chemical mechanical polishing carrier head that includes a retaining ring, and associated methods.
Integrated circuits are typically formed on substrates, particularly silicon wafers, by the sequential deposition of conductive, semiconductive or insulative layers. After each layer is deposited, it is etched to create circuitry features. As a series of layers are sequentially deposited and etched, the exposed surface of the substrate becomes increasingly nonplanar. This nonplanar surface presents problems in the photolithographic steps of the integrated circuit fabrication process. Therefore, there is a need to periodically planarize the substrate surface.
One accepted method of planarization is chemical mechanical polishing (CMP). This planarization method typically requires that the substrate be mounted on a carrier or polishing head. The exposed surface of the substrate is placed against a moving polishing surface, such as a rotating polishing pad. The polishing pad may be a “standard” polishing pad with a durable roughened surface or a “fixed-abrasive” polishing pad with abrasive particles held in a containment media. The carrier head provides a controllable load to the substrate to push it against the polishing pad. A polishing slurry, which may include abrasive particles, is supplied to the surface of the polishing pad.
The effectiveness of a CMP process may be measured by its polishing rate and by the resulting finish (absence of small-scale roughness) and flatness (absence of large-scale topography) of the substrate surface. The polishing rate, finish and flatness are determined by the pad and slurry combination, the relative speed between the substrate and pad, and the force pressing the substrate against the polishing pad.
A reoccurring problem in CMP is the so-called “edge-effect”, i.e., the tendency for the edge of the substrate to be polished at a different rate than the center of the substrate. The edge effect typically results in over-polishing (the removal of too much material from the substrate) of the perimeter portion, e.g., the outermost five to ten millimeters, of the substrate. The over-polishing of the substrate perimeter reduces the overall flatness of the substrate, makes the edge of the substrate unsuitable for use in integrated circuits, and decreases the yield.